Method For Increasing Storage Capacity of a Memory Device

ABSTRACT

A method for increasing memory storage capacity in a memory device having at least two storage cells wherein at least one measurable physical property is associated with each of the storage cells a nominal value of which may be used to assign a data value to the respective storage cell. Differences between at least two storage cells with regard to the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time are used to provide additional storage capacity.

FIELD OF THE INVENTION

This invention relates to memory devices.

BACKGROUND OF THE INVENTION

A data storage (memory) circuit is a circuit that enables keeping/holding a certain amount of information within a physical place (cell), with the ability of later extraction/reading of the information. Moreover, one can generalize the above definition by treating the memory as an information container in physical space-time (rather than in physical space only). Then, it is more natural to understand some of the physical processes involved in data storage. The time dimension differs between some of the features of different types of memory circuits.

Information, in its modern understanding was realized in the first half of the 20^(th) century, by the pioneering works of Nyquist & Shennon. The deep understanding of the relation to physics is the foundation of modern information & communication theory. Nyquist was the first one to understand the sampling issue, while Shannon was the first one to understand the relation of information to the physical term—“entropy” (that was realized first by Boltzmann at the end of the 19^(th) century).

Conventionally, memory devices are digital circuits that stores data digitally in binary form. The number of cells in the memory device determines the number (n) of bits that can be stored in such a memory. The number of bits determines the number (S) of states that can be stored such that n=log₂S.

It emerges from the above that every additional bit doubles the number of states, i.e. the capacity of the memory device. In the ever increasing drive to increase the storage capacity of memory devices, much effort has been invested in making the circuits themselves more compact and to improving methods of mass production. This has resulted in a dramatic increase in the performance/cost ratio of memory devices in recent years.

However, since the number of states of the memory (i.e. its storage capacity) is determined by the number of bits (i.e. cells in a digital memory), the storage capacities of known memory devices are limited by the number of cells. It is clearly desirable to increase the storage capacity of a memory without adding storage cells.

This desideratum is known per se. Thus, it is known to increase the density of flash memories using Multi-Level-Cell (M.L.C.) technology. This technology lowers the cost by enabling the storage of multiple bits of data per memory cell thereby reducing the consumption of silicon area. This technology is used by various manufacturers of flash memory such as the Intel StrataFlash memory as described by Greg Atwood et al. in the Intel Technology Journal Q4, 1997. As described therein, a flash memory device is a single transistor that includes an isolated floating gate. The floating gate is capable of storing electrons. The behavior of the transistor is altered depending on the amount of charge stored on the floating gate. Charge is placed on the floating gate through a technique called programming. The programming operation generates hot electrons in the channel region of the memory cell transistor. A fraction of these hot electrons gain enough energy to surmount the 3.2 eV barrier of the Si—SiO₂ interface and become trapped on the floating gate. For single bit per cell devices, the transistor either has little charge (<5,000 electrons) on the floating gate and thus stores a “1” or it has a lot of charge (>30,000 electrons) on the floating gate and thus stores a “0.” When the memory cell is read, the presence or absence of charge is determined by sensing the change in the behavior of the memory transistor due to the stored charge. The stored charge is manifested as a change in the threshold voltage of the memory cell transistor.

It is thus known to compare a physical property associated with a memory cell with an external reference in order to associate multiple states with a single memory cell. It would be desirable to provide a method for increasing the storage capacity of a memory device having a given number of memory cells and a given number of levels of a physically limited external reference.

SUMMARY OF THE INVENTION

It is therefore a principal object of the invention to increase the storage capacity of a memory device having a given number of memory cells and a given number of levels of a physically limited external reference.

It is a further object of the invention to provide a method of increasing the number of states, so as to increase the number of bits within a memory chip but without increasing the number of memory cells and without the need to employ an extra external reference state as is done in MLC where the external reference serves to define the actual logic value to be associated with each storage cell.

These objects are realized in accordance with an aspect of the invention by a method for increasing storage capacity of a predetermined number of storage cells in a memory device having at least two storage cells, the method comprising:

-   -   (a) associating with each of the storage cells at least one         measurable physical property whose nominal value may be used to         assign a data value to the respective storage cell; and     -   (b) using differences between the respective nominal values of         one or more of the respective physical properties associated         with a storage cell and its actual value at a given time to         provide additional storage capacity.

In accordance with such a method, the number of physical states within a system of memory cells is increased based on inter-relations between cells. Such a method can be integrated with all other methods implemented to further increase the number of bits per given number of physical memory cells.

DETAILED DESCRIPTION OF AN EXEMPLARY EMBODIMENT Fundamental Principles

We start our explanation with the simplest example—two physical cells and a defined observable order in which data is written to the cells. Thus, two bits and an order provide states as shown in Table I below:

TABLE I

Within the above 16 states, equal ordered states (EOS) permitted. In the case that only non-equal ordered states (NEOS) allowed, only 8 states exist (i.e. only states no. 2, 3, 6, 7, 10, 11, 14, 15).

Yet, another option for 8-Selection of “type-2” is the states: 1, 2, 3, 5, 9, 13, 14, 15. In “type-2” selection, the order plays a role, if and only if the two bits are equal and of different order.

So in the EOS case, the 16 states are equivalent to 4 Bits (i.e. 2⁴ states), while in the NEOS case and the “type-2” selection one gets 3 Bits (i.e. 8=2³ states).

The key issue demonstrated in the above example is that by associating a defined observable order of writing data to two physical bits provides two extra bits in the EOS case and one extra Bit in the NEOS case or in the “type-2” case.

Consider now the situation of three physical bits and an observable Order. We will make use of the following acronyms: Or—order, St—States, B—Physical Bit.

Table II below there are the 27 states of the (0, 0, 0) combination due to 3-Order.

TABLE II

Since, there are originally 8 states in the 3 Physical Bits (000, 001, 010, 011, 100, 101, 110, 111) then taking in account the 3-Order, one gets:

For the EOS case the number of states is 2³×3³=8×27=216 states 2^(7.755) That is more than 7 Bits and less than 8 Bits.

For the NEOS case the number of states is 2³×3!=8×6=48 states≠2^(5.585)

That is more than 5 Bits and less than 6 Bits.

As a rule the total number of states for N Physical Bits and N-Order is:

For the EOS case—2^(N)×N^(N)

For the NEOS case—2^(N)×N!

The first few cases are summarized in Table III below:

TABLE III EOS NEOS N Bits Bits 2 4 3 3 7.754888 5.584963 4 12 8.584963 5 16.60964 11.90689 6 21.50978 15.49185 7 26.65148 19.29921 8 32 23.29921

Remark: Without losing the generality, the Order can be of different number than the number of bits.

Order

It is to be noted that although “order” is used in the above examples to show how additional information may be associated with a pair of bits so as to thereby increase the storage capacity, this is merely to demonstrate the concept of the invention. In practice, the order of writing data need not be (and generally is not) determined and instead there may be associated with different cells a measurable physical property whose value is dependent on the order in which the data is written, although the order is not required explicitly. It thus emerges that no physical clock is provided for associating time associated with physical properties: rather time may be inferred from the measurement of physical properties whose values are time-dependent. Moreover, although in the specific examples provided, the term “order” has been given temporal significance (i.e. is defined by the time sequence in which data is written), this also is by way of example only. In practice, there may be used any ordered parameter in connection with which it is possible to apply comparison operators such as ‘<’, ‘>’, ‘=’, ‘≠’, ‘≈’ ‘≦’, ‘≧’ and so on and providing that the application of these operators on the respective properties between cells yields the same results.

Yet another consideration is that, in practice, data need not actually be written in a time-dependent order in order to extend the storage capacity of the memory device providing that the measured physical properties of different cells within the device are different and that the difference may be construed as a difference in the temporal order in which data was written to the cells. For example, DDR (Double Data Rate) memory uses SDRAM i.e. Synchronous Dynamic RAM, that can run at much higher clock speeds than conventional memory so as to effectively double transfer rate. SDRAM is volatile and so must be constantly energized and refreshed, typically 1,000 times per second. SDRAM cells operate in a manner analogous to capacitors whose charge produces a voltage that is indicative of a logic level to be associated with the cell. The storage capacity of SDRAM may be increased in accordance with the invention by using the voltage on each cell of the memory as an ordered parameter. Thus consider the simple case of two bits of SDRAM and suppose that a logic “1” bit is represented by any voltage that exceeds V_(REF). In such case, providing the memory cells are refreshed before the voltage of a cell whose logic level is to be construed as “1” does not fall below V_(REF), the data integrity of the cell will be maintained. However, since the actual voltage of the cell is immaterial (providing only that it is greater than V_(REF) for logic “1”) it is not necessary to refresh different cells at different times so as to associate a different temporal order with the cells that may then be used to provide additional bits of data storage. Rather, instead of refreshing cells with a constant voltage at different times, cells may be refreshed simultaneously but with varying voltages whose gradient may be construed as a time-ordered sequence.

Moreover, it will be understood that in such an application the apparent “order” associated with different cells in the memory device is generated when writing the data to the cells but is actually derived when the data is read. This is generally true whenever the order is not determined explicitly but is derived from the values of respective physical properties associated with different cells in the memory device.

In the following we will mention some non-limiting physical properties that may be used to define the Order feature associated with data in the storage cells:

1. Directional Potential Differences.

2. Directional Charge Current.

3. Time Voltage Decaying and/or Time Charge decaying.

4. Aging

5. Magnetic intensity

6. Optical intensity

7. Electromagnetic frequency.

As distinct from hitherto-proposed memory storage methods, the method according to the invention makes use of not only on “global” voltage reference values, but on relative values in between a set of bits.

The relative values provide the extra information, which is equivalent to extra bits.

The order in which data is written adds the dimension of time to the storage device whose physical cells define the dimension of space. Thus, the invention allows data to be stored in space-time rather than space only as provided for in known memory devices and storage methods.

The relativity of the physical values in between bits enables us to be more flexible, since the relative value of the observables, is the extra source of information. Therefore, GT—Greater Than, LT—Less Than, Eq—(almost) Equal, i.e. comparator operations are the needed operations for extracting the extra information.

The cost in the Space-Time storage method according to the invention is that more operations must be performed before the data is extracted or stored. However, the benefit is that more data can be stored. So while the total time delay might be increased, in practice it is much less than what might be expected.

Another cost might be due to the fact that the relative values of the bits should be preserved. So if the method of the invention is implemented in e.g. DDR, the process for refreshing values should maintain not only the absolute values of the storage cell, but also the relative values (or relative comparative relation) in between the bits, which serve to associate an apparent order with the cells. This is a more complicated process, although the cost benefits are the additional storage capacity.

It is to be understood that the method for increasing storage capacity of a memory device is applicable to any memory device for which a physical property may be associated with the storage cells thereof such that discrete variations in the physical property may serve to associate an apparent order in writing data to at least some of the storage cells in the memory device. The invention therefore embraces any such memory device that is configured for applying the method. Thus, the invention may be employed in any of the following memory devices, among others: RAM, DRAM, SRAM, SDRAM, DDR-I, DDR-II, DDR-III, RDRAM, FLASH, FCRAM, MRAM, Optic memory, CD, DVD, ROM, PROM, EPROM, E²PROM.

It will also be appreciated that such memory devices may themselves be part of composite processing units and devices such as CPU, GPU, DSP, FPGA, ASIC, FPGA, Network processor, A/D chips, D/A chips, Video chips, Voices chips, Logic devices, SD Card, Compact Flash, Smart-Media, PC-Card, Disk-On-Key, Dimm, Sim, PC, Mobile Phone, PDA, Remote Controller. 

1-16. (canceled)
 17. A method for increasing storage capacity of a predetermined number of storage cells in a memory device having at least two storage cells, the method comprising: (a) associating with each of the storage cells at least one measurable physical property whose nominal value may be used to assign a data value to the respective storage cell; and (b) using differences between the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time to provide additional storage capacity.
 18. The method according to claim Error! Reference source not found. 7, wherein said at least one measurable physical property is compared in respect of a constant or variable number of storage cells greater than two.
 19. The method according to claim Error! Reference source not found. 7, wherein the at least one measurable physical property is included in the group comprising: electric charge, current, voltage, decay time, magnetic intensity, optical intensity, electromagnetic frequency.
 20. The method according to claim Error! Reference source not found. 7, further including bidirectional data encoding and/or decoding.
 21. The method according to claim Error! Reference source not found. 7, wherein respective physical properties associated with a storage cell are used to determine an order of writing bits to respective groups of cells of the storage device and the order associated with respective groups of cells is used to add at least one further bit in respect of the respective group of cells.
 22. The method according to claim 21, wherein said order is inferred from values of said physical properties.
 23. The method according to claim 21, wherein the order associated with at least two cells is not used to allocate at least one further bit to the memory device.
 24. The method according to claim 23, including selectively configuring groups of cells in the memory device for enabling or disabling allocation of an order-dependent bit.
 25. The method according to claim 21, wherein the number of possible order states is different than the number of said further bits.
 26. A method for increasing the information-storage-capabilities of a given number greater or equal to two, of storage cells (i.e. memory cells) based on in-between storage cells comparison.
 27. The method according to claim 26, further including bidirectional data encoding and/or decoding.
 28. The method according to claim 26, wherein respective physical properties associated with a storage cell are used to determine an order of writing bits to respective groups of cells of the storage device and the order associated with respective groups of cells is used to add at least one further bit in respect of the respective group of cells.
 29. The method according to claim 28, wherein said order is inferred from values of said physical properties.
 30. The method according to claim 28, wherein the order associated with at least two cells is not used to allocate at least one further bit to the memory device.
 31. The method according to claim 30, including selectively configuring groups of cells in the memory device for enabling or disabling allocation of an order-dependent bit.
 32. The method according to claim 28, wherein the number of possible order states is different than the number of said further bits.
 33. A memory device having at least two storage cells and being configured to associate with said storage cells additional states, by performing the following: (c) associating with each of the storage cells at least one measurable physical property whose nominal value may be used to assign a data value to the respective storage cell; and (d) using differences between the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time to provide additional storage capacity.
 34. The memory device according to claim 33, wherein the storage cells are configured to contain one bit per cell (i.e. two states) or more than one bit per cell.
 35. The memory device according to claim 33, being in the group: RAM, DRAM, SRAM, SDRAM, DDR-T, DDR-TT, DDR-TTT, RDRAM, FLASH, FCRAM, MRAM, Optic memory, CD, DVD, ROM, PROM, EPROM, E²PROM.
 36. A memory device having at least two storage cells (i.e. memory cells) and being configured to associate with said storage cells additional states by performing a method based on in-between storage cells comparison.
 37. The memory device according to claim 36, wherein the storage cells are configured to contain one bit per cell (i.e. two states) or more than one bit per cell.
 38. The memory device according to claim 36, being in the group: RAM, DRAM, SRAM, SDRAM, DDR-T, DDR-TT, DDR-TTT, RDRAM, FLASH, FCRAM, MRAM, Optic memory, CD, DVD, ROM, PROM, EPROM, E²PROM.
 39. An electronic device containing a memory device having at least two storage cells and being configured to associate with said storage cells additional states, by performing the following: (e) associating with each of the storage cells at least one measurable physical property whose nominal value may be used to assign a data value to the respective storage cell; and (f) using differences between the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time to provide additional storage capacity.
 40. The electronic device according to claim 39, being in the group: CPU, GPU, DSP, FPGA, ASIC, FPGA, Network processor, A/D chips, D/A chips, Video chips, Voices chips, Logic devices, SD-Card, Compact Flash, Smart-Media, PC Card.
 41. An electronic device containing a memory device having at least two storage cells (i.e. memory cells) and being configured to associate with said storage cells additional states by performing a method based on in-between storage cells comparison.
 42. The electronic device according to claim 41, being in the group: CPU, GPU, DSP, FPGA, ASIC, FPGA, Network processor, A/D chips, D/A chips, Video chips, Voices chips, Logic devices, SD-Card, Compact Flash, Smart-Media, PC Card.
 43. A hardware assembly containing a memory device having at least two storage cells and being configured to associate with said storage cells additional states, by performing the following: (g) associating with each of the storage cells at least one measurable physical property whose nominal value may be used to assign a data value to the respective storage cell; and (h) using differences between the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time to provide additional storage capacity.
 44. A hardware assembly containing a memory device having at least two storage cells (i.e. memory cells) and being configured to associate with said storage cells additional states by performing a method based on in-between storage cells comparison.
 45. A hardware assembly containing an electronic device which contains a memory device having at least two storage cells and being configured to associate with said storage cells additional states, by performing the following: (i) associating with each of the storage cells at least one measurable physical property whose nominal value may be used to assign a data value to the respective storage cell; and (j) using differences between the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time to provide additional storage capacity
 46. A hardware assembly containing an electronic device which contains a memory device having at least two storage cells (i.e. memory cells) and being configured to associate with said storage cells additional states by performing a method based on in-between storage cells comparison. 